1. Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, particularly to a method of increasing the source/drain contact area, and more particularly to a method of forming a silicided poly spacer for enhanced contact area.
2. Description of Related Art
Transistor fabrication in a smaller size allows a MOS integrated circuit to operate at higher speed. However, the smaller size poses new problems in fabrication and operation. In sub-micron integrated circuit technology, parameters such as source/drain contact area are continually being reduced. In order to enhance the quality of an integrated circuit chip, a silicide layer is formed to reduce the contact resistance at the gate and the source/drain region. The conventional silicide formation process includes simultaneously forming silicide on the source/drain silicon and on the gate polysilicon.
Device roll-off requirements generally demand a 50 nm wide spacer be used for the deep junction implants. However, ground rules typically call for a 192 nm gate poly pitch and a 35 nm physical gate length. This leaves inadequate spacing between minimally spaced gates to align and squarely land contacts on the diffusion between gates, mostly because the area over the source/drain extensions is unavailable to make contact. Landing on the spacer or on the underlying LTO leads to high contact resistance, since this portion of the contact is electrically insulated. Furthermore, trying to etch through these insulators and land on the shallow LDD extension results in punch-through of the contact through the extension profile, and causes high junction leakages. Since CA nitride RIE is designed to stop on silicide, silicide forms an ideal etch-stop. Consequently, landing on the contact on silicide ensures a good electrical connection.
SRAM designs use elongated contacts to strap the gate and the adjacent diffusion of cell device. Printing and etching these elongated CA bars is an on-going challenge in the art. The ability to strap the gate and diffusion with a regularly shaped contact would circumvent these issues.
In U.S. Pat. No. 6,566,208 issued to Pan, et al., on May 20, 2003 entitled, “METHOD TO FORM ELEVATED SOURCE/DRAIN USING POLY SPACER,” a gate electrode is formed over a gate dielectric on a semiconductor substrate. A polysilicon layer is deposited overlying the semiconductor substrate, gate electrode, and dielectric spacers wherein the polysilicon layer is heavily doped. The polysilicon layer is then etched back to leave polysilicon spacers.
In U.S. Pat. No. 6,169,017 issued to Lee on Jan. 2, 2001 entitled, “METHOD TO INCREASE CONTACT AREA,” a fabrication method is taught to increase the gate contact area in which two sacrificial layers are formed on a silicon substrate, where the surface of the second sacrificial layer is lower than the top of the polysilicon gate by a certain thickness. A silicidation process is conducted to form a silicide layer on the gate structure and a side-wing polysilicon layer to lower the gate contact resistance. The side-wing polysilicon layer is formed on both sides of the gate to increase the area for a silicide formation.